The present invention relates to computer memory interface circuitry in general, and more particularly to the sorting of requests for efficient access to memories.
Memory devices are fast becoming a bottleneck and limiting improvements in computer system performance. Part of this is caused by the relative disparity between the increase in processor as compared to memory speed. That is, while processor speed has continued to increase at the well known rate of doubling every 18 to 24 months, memory access times have not kept pace. This gap means that more efficient use of memory bandwidth must be made in order to reduce the effect of this bottleneck and take full advantage of the improved processor performance.
Memories in computer systems are often made up of multiple dynamic random-access-memory (DRAM) circuits, partitioned into banks, which may be located in dual-in-line memory modules (DIMMs). To access data in a DRAM at a given row/bank/column address, the bank must first be opened (activated) to the desired row. A read or write command or request can then be issued to the bank/column address, implicitly using the row address which is associated with the open bank. A specific row/bank is a page. If a subsequent access requires a different row within the same bank (a “page fault” or “page break”), then the bank must first be closed (precharged) before it can be opened (activated) to the new row. The activate and precharge latencies for a given bank require sufficient amounts of data transfers to other banks in order to hide them. To the extent that these latencies are not hidden, penalties arise in the form of idle cycles which limit the effective bandwidth.
Therefore, it is desirable to have methods and systems for sorting memory requests, for example, to increase the effective bandwidth.